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0V to 16V, Dual Hot-Swap Controller with 10-Bit
Current and Voltage Monitor and 4 LED Drivers
Table 4a. status1 Register Function
REGISTER
ADDRESS
0x32
BIT
RANGE
[1:0]
[4]
[7:6]
DESCRIPTION
ON_ Inputs State
1 = ON_ above 600mV channel enable threshold
0 = ON_ below 600mV channel enable threshold
Bit 0: ON1
Bit 1: ON2
Channel Grouping Mode (MODE Input)
0 = Grouped (MODE high or open)
1 = Independent (MODE low)
Voltage Critical Behavior (PROT Input)
00 = Assert ALERT upon UV/OV critical (same as UV/OV warning behavior)
01 = Assert ALERT and deassert PG_ upon UV/OV critical
10 = Assert ALERT , deassert PG_, and shutdown channel(s) upon UV/OV critical
11 = (Not possible)
Table 4b. status1 Register Format
Description:
Register Title:
Register Address:
Channel grouping (three-state MODE input), fault-detection behavior (three-state PROT input), and
ON_ inputs status register
status1
0x32
R
prot[1]
bit 7
R
prot[0]
bit 6
R
—
bit 5
R
mode[0]
bit 4
R
—
bit 3
R
—
bit 2
R
ON2
bit 1
R
ON1
bit 0
RESET
VALUE
0x00
Figure 1 shows the detailed logic operation of the hot-
swap enable signals Chx_EN1, Chx_EN2, and ON_, as
well as the effect of various fault conditions.
An input undervoltage threshold control for enabling
the hot-swap channel can be implemented by placing
a resistive divider between the drain of the hot-swap
MOSFET and ground, with the midpoint connected to
ON_. The turn-on threshold voltage for the channel is
then:
V EN = 0.6V x (R1 + R2)/R2
The maximum rating for the ON_ is 6V; do not exceed
this value.
Startup
When all conditions for channel turn-on are met, the
external n-channel MOSFET switch is fully enhanced
with a typical gate-to-source voltage of 5V to ensure
a low drain-to-source resistance. The charge pump at
each GATE_ driver sources 5 F A to control the output
voltage turn-on voltage slew rate. An external capacitor
can be added from GATE_ to GND_ to further reduce the
voltage slew rate. Placing a 1k I resistor in series with
this capacitance prevents the added capacitance from
increasing the gate turn-off time. Total inrush current is
the load current summed with the product of the gate
voltage slew rate dV/dt and the load capacitance.
______________________________________________________________________________________
15
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